Track-and-Hold Circuit

ABSTRACT

A track-and-hold circuit includes: a transistor, in which a base is connected to a signal input terminal, a power supply voltage is applied to a collector, and an emitter is connected to a first signal output terminal; a transistor in which a base is connected to the signal input terminal, the power supply voltage is applied to a collector, and an emitter is connected to a second signal output terminal; capacitors; a constant current source; and a switch circuit alternately turning the transistors to an ON state in response to differential clock signals.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national phase entry of PCT Application No.PCT/JP2020/002895, filed on Jan. 28, 2020, which application is herebyincorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a track-and-hold circuit thatalternately repeats track modes and hold modes at the timingsynchronized with a clock signal.

BACKGROUND

Analogue-to-digital converters (ADCs) are widely used devices forcommunication and measurement. The ADC converts the input voltage, whichis an analogue signal, into a quantized digital value at the timingsynchronized with a clock signal and outputs a digital code thereof. Inmany cases, the ADC often includes a track-and-hold circuit at a frontend portion (refer to Non-Patent Literature 1).

As shown in FIG. 5 , a track-and-hold circuit 100 is a circuit thatalternately repeats a track mode Mt, in which the output signal Voutfollows the input signal Vin, and a hold mode Mh, which keeps the outputsignal Vout constant, at the timing synchronized with a clock signalVck.

One of the reasons why the track-and-hold circuit is used at the frontend portion of the ADC is that the ADC takes a certain amount of timefor analogue-to-digital conversion, and therefore, it is necessary toretain the input signal during the conversion.

Another reason to use the track-and-hold circuit at the front endportion of the ADC is to reduce the noise effect by clock jitter. Sincethe timing of the clock signal is not at perfectly equal time intervals,statistical variation occurs in the timing of retaining the inputsignal. If there is such clock jitter, the output from the ADC isobserved as if noise is superimposed thereon.

By using a track-and-hold circuit with very low clock jitter at thefront end portion, even if the clock jitter occurs slightly in the ADCin the latter part, there is no noise effect if the clock jitter iswithin a hold time of the track-and-hold circuit.

Since, in particular, the latest state-of-the-art ADCs are difficult toreduce the clock jitter, the ADCs cannot increase the speed thereofwhile keeping noise levels within a practical range; accordingly, theclock jitter is the factor in inhibiting speeding up. Therefore,speeding up of the track-and-hold circuit is effective for speeding upof the ADC.

In many cases, an analogue circuit is configured by connecting switchingelements called transistors, resistors, capacitors, and so on. There areseveral types of transistors, but bipolar transistors are often used inanalogue circuits in which high-speed operation is required. As acircuit configuration for the existing track-and-hold circuits using thebipolar transistors, those called switched emitter followers are wellknown.

A typical configuration of a conventional track-and-hold circuit usingbipolar transistors is shown in FIG. 6 . In FIG. 6 , VCC and VEE arepower supply voltages, Vin is an input signal, Vout is an output signal,and Vck+ and Vck− are clock signals. The clock signals Vck+ and Vck− aredifferential signals. In addition, (const.) in FIG. 6 indicates that thevoltage or the current is constant regardless of time.

The track-and-hold circuit is configured of bipolar transistors M10 toM12, a capacitor Chold, and a constant current source IS. The constantcurrent source IS is configured of transistors, and so on in many cases.IEE1 and IEE2 are currents flowing into the constant current source ISfrom the emitters of the bipolar transistors M11 and M12. Assuming thatthe current flowing to the constant current source IS is IEE, thenIEE1+IEE2=IEE due to Kirchhoff's current law.

The basic operation of the track-and-hold circuit in FIG. 6 will bedescribed using FIGS. 7A to 7E. Here, the waveforms of the currents IEE1and IEE2, when the differential clock signals Vck+ and Vck− with aperiod Tck shown in FIG. 7A and the input signal Vin shown in FIG. 7Bare applied to the track-and-hold circuit, are shown in FIGS. 7C and 7D,and the waveform of the output signal Vout is shown in FIG. 7E. In FIGS.7A to 7E, t0, t1, t2, t3, and t4 represent times. The times t0 to t4 arearranged with constant intervals Tck/2.

When the clock signal is High, that is, Vck+>Vck− (when the time tsatisfies t0≤t≤t1 or t2≤t≤t3), the transistor M11 is turned OFF and thetransistor M12 is turned ON; therefore, IEE1=IEE, and IEE2=0. At thistime, since the PN junction between the base and the emitter of thetransistor M10 is in the ON state, the emitter voltage of the transistorM10 (the output signal Vout) follows the input signal Vin. In otherwords, when the time t satisfies t0≤t≤t1 or t2≤t≤t3, the track-and-holdcircuit is in the track mode.

On the other hand, when the clock signal is Low, that is, Vck+<Vck−(when the time t satisfies t1≤t≤t2 or t3≤t≤t4), the transistor M11 isturned ON and the transistor M12 is turned OFF; therefore, IEE1=0, andIEE2=IEE. Consequently, since no current flows to the transistor M10 andthe PN junction between the base and the emitter of the transistor M10is in the OFF state, the base and the emitter of the transistor M10 areelectrically separated. At this time, the emitter voltage of thetransistor M10 (the output signal Vout) at the moment when the clocksignal changes from High to Low is retained in the capacitor Chold;therefore, the output signal Vout is kept at a constant value while theclock signal is Low. In other words, when the time t satisfies t1≤t≤t2or t3≤t≤t4, the track-and-hold circuit is in the hold mode.

As described above, the basic operation of the track-and-hold circuit isto alternately repeat the track mode and the hold mode in accordancewith High/Low of the clock signal.

It is clear that the data rate of the track-and-hold circuit, that is,the number of times to obtain data per unit time, depends on the clockfrequency. However, due to the constraint conditions of the analoguecircuits, specifically, parasitic resistance and parasitic capacitanceexisting in transistors and wiring, the frequency of the clock signalthat can be inputted has an upper limit. The upper limit of thefrequency of the clock signal is a main factor in limiting the speed ofthe track-and-hold circuit.

CITATION LIST Non-Patent Literature

-   Non-Patent Literature 1: S. Yamanaka, K. Sano, and K. Murata, “A    20-Gs/s Track-and-Hold Amplifier in InP HBT Technology,” in IEEE    Transactions on Microwave Theory and Techniques, vol. 58, No. 9, pp.    2334-2339, September 2010.

SUMMARY Technical Problem

Embodiments of the present invention have been made to solve the aboveproblems, and has as an object to speed up the data rate of thetrack-and-hold circuit.

Means for Solving the Problem

A track-and-hold circuit of embodiments of the present inventionincludes: a first transistor, in which a base is connected to a signalinput terminal, a power supply voltage is applied to a collector, and anemitter is connected to a first signal output terminal; a secondtransistor, in which a base is connected to the signal input terminal,the power supply voltage is applied to a collector, and an emitter isconnected to a second signal output terminal; a first capacitor, one endof which is connected to the collector of the first transistor, and theother end of which is connected to the emitter of the first transistor;a second capacitor, one end of which is connected to the collector ofthe second transistor, and the other end of which is connected to theemitter of the second transistor; a constant current source configuredto supply a constant current to the first and second transistors; and aswitch circuit connected between the emitters of the first and secondtransistors and the constant current source, and is configured toalternately turn the first and second transistors to an ON state inresponse to differential clock signals.

Moreover, in a configuration example of the track-and-hold circuit ofembodiments of the present invention, the switch circuit is configuredof: a third transistor, in which a base is connected to a positive-phaseclock input terminal, a collector is connected to the emitter of thefirst transistor, and an emitter is connected to the constant currentsource; and a fourth transistor, in which a base is connected to anegative-phase clock input terminal, a collector is connected to theemitter of the second transistor, and an emitter is connected to theconstant current source.

Moreover, a track-and-hold circuit of embodiments of the presentinvention includes: a first transistor, in which a base is connected toa positive-phase signal input terminal, a power supply voltage isapplied to a collector, and an emitter is connected to a firstpositive-phase signal output terminal; a second transistor, in which abase is connected to a negative-phase signal input terminal, the powersupply voltage is applied to a collector, and an emitter is connected toa first negative-phase signal output terminal; a third transistor, inwhich a base is connected to the positive-phase signal input terminal,the power supply voltage is applied to a collector, and an emitter isconnected to a second positive-phase signal output terminal; a fourthtransistor, in which a base is connected to the negative-phase signalinput terminal, the power supply voltage is applied to a collector, andan emitter is connected to a second negative-phase signal outputterminal; a first capacitor, one end of which is connected to thecollector of the first transistor, and the other end of which isconnected to the emitter of the first transistor; a second capacitor,one end of which is connected to the collector of the second transistor,and the other end of which is connected to the emitter of the secondtransistor; a third capacitor, one end of which is connected to thecollector of the third transistor, and the other end of which isconnected to the emitter of the third transistor; a fourth capacitor,one end of which is connected to the collector of the fourth transistor,and the other end of which is connected to the emitter of the fourthtransistor; a constant current source configured to supply a constantcurrent to the first, second, third, and fourth transistors; and aswitch circuit connected between the emitters of the first, second,third, and fourth transistors and the constant current source, and isconfigured to alternately turn a first differential circuit comprisingthe first and second transistors and a second differential circuitcomprising the third and fourth transistors to an ON state in responseto differential clock signals.

Moreover, in a configuration example of the track-and-hold circuit ofembodiments of the present invention, the switch circuit is configuredof: a fifth transistor, in which a base is connected to a positive-phaseclock input terminal, a collector is connected to the emitter of thefirst transistor, and an emitter is connected to the constant currentsource; a sixth transistor, in which a base is connected to thepositive-phase clock input terminal, a collector is connected to theemitter of the second transistor, and an emitter is connected to theconstant current source; a seventh transistor, in which a base isconnected to a negative-phase clock input terminal, a collector isconnected to the emitter of the third transistor, and an emitter isconnected to the constant current source; and an eighth transistor, inwhich a base is connected to the negative-phase clock input terminal, acollector is connected to the emitter of the fourth transistor, and anemitter is connected to the constant current source.

Effects of Embodiments of the Invention

According to embodiments of the present invention, by alternatelyturning the first and second transistors to the ON state in response tothe differential clock signals, it is possible to switch the circuit toenter the track mode and the circuit to enter the hold mode every halfperiod of the differential clock signal, and thereby the data rate twiceas high as that of the conventional track-and-hold circuit can beachieved.

Moreover, in embodiments of the present invention, by alternatelyturning the first differential circuit configured of the first andsecond transistors and the second differential circuit configured of thethird and fourth transistors to the ON state in response to thedifferential clock signals, it is possible to switch the differentialcircuit to enter the track mode and the differential circuit to enterthe hold mode every half period of the clock signal, and thereby thedata rate twice as high as that of the conventional track-and-holdcircuit can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a configuration of a track-and-holdcircuit related to a first embodiment of the present invention.

FIGS. 2A to 2F are diagrams showing signal waveforms of each part of thetrack-and-hold circuit related to the first embodiment of the presentinvention.

FIG. 3 is a circuit diagram showing a configuration of a track-and-holdcircuit related to a second embodiment of the present invention.

FIGS. 4A to 4G are diagrams showing signal waveforms of each part of thetrack-and-hold circuit related to the second embodiment of the presentinvention.

FIG. 5 is a diagram conceptually illustrating the configuration andoperation of the track-and-hold circuit.

FIG. 6 is a circuit diagram showing a configuration of a conventionaltrack-and-hold circuit.

FIGS. 7A to 7E are diagrams showing signal waveforms of each part of theconventional track-and-hold circuit.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS First Embodiment

Hereinafter, embodiments of the present invention will be described withreference to drawings. FIG. 1 is a circuit diagram showing aconfiguration of a track-and-hold circuit related to a first embodimentof the present invention. In FIG. 1 , VCC and VEE are power supplyvoltages, Vin is an input signal, Vout is an output signal, and Vck+ andVck− are clock signals. The clock signals Vck+ and Vck− are differentialsignals. In addition, (const.) in FIG. 1 indicates that the voltage orthe current is constant regardless of time.

The track-and-hold circuit of the embodiment includes: a bipolartransistor M1, in which a base is connected to a signal input terminal(Vin), a power supply voltage VCC is applied to a collector, and anemitter is connected to a first signal output terminal (Vout1); abipolar transistor M2, in which a base is connected to a positive-phaseclock input terminal (Vck+), and a collector is connected to the emitterof the bipolar transistor M1; a bipolar transistor M3, in which a baseis connected to the signal input terminal (Vin), the power supplyvoltage VCC is applied to a collector, and an emitter is connected to asecond signal output terminal (Vout2); and a bipolar transistor M4, inwhich a base is connected to a negative-phase clock input terminal(Vck−), and a collector is connected to the emitter of the bipolartransistor M3.

Further, the track-and-hold circuit also includes: a capacitor Chold1,one end of which is connected to the collector of the bipolar transistorM1 and the other end of which is connected to the emitter of the bipolartransistor M1; a capacitor Chold2, one end of which is connected to thecollector of the bipolar transistor M3 and the other end of which isconnected to the emitter of the bipolar transistor M3; and a constantcurrent source IS, one end of which is connected to the emitters of thebipolar transistors M2 and M4 and the other end of which is connected toa power supply voltage VEE.

The constant current source IS is configured of transistors, etc., inmany cases. IEE1 and IEE2 are currents flowing into the constant currentsource IS from the emitters of the bipolar transistors M2 and M4.Assuming that the current flowing to the constant current source IS isIEE, then IEE1+IEE2=IEE due to Kirchhoff's current law.

The transistors M2 and M4 constitute a switch circuit SW1 thatalternately turns the transistors M1 and M2 to the ON state in responseto the differential clock signals Vck+ and Vck−.

The basic operation of the track-and-hold circuit in FIG. 1 will bedescribed using FIGS. 2A to 2F. Here, the waveforms of the currents IEE1and IEE2, when the differential clock signals Vck+ and Vck− with aperiod Tck shown in FIG. 2A and the input signal Vin shown in FIG. 2Bare applied to the track-and-hold circuit, are shown in FIGS. 2C and 2D,and the waveforms of the output signals Vout1 and Vout2 at that time areshown in FIGS. 2E and 2F. In FIGS. 2A to 2F, t0, t1, t2, t3, and t4represent times. The times t0 to t4 are arranged with constant intervalsTck/2.

When the clock signal is High, that is, Vck+>Vck− (when the time tsatisfies t0≤t≤t1 or t2≤t≤t3), the transistor M2 is turned ON and thetransistor M4 is turned OFF; therefore, IEE1=IEE, and IEE2=0. At thistime, since the PN junction between the base and the emitter of thetransistor M1 is in the ON state, the emitter voltage of the transistorM1 (the output signal Vout1) follows the input signal Vin.

On the other hand, since no current flows to the transistors M3 and M4,the PN junction between the base and the emitter of the transistor M3 isin the OFF state, and the base and the emitter of the transistor M3 areelectrically separated. At this time, the emitter voltage of thetransistor M3 (the output signal Vout2) at the moment when the clocksignal changes from Low to High is retained in the capacitor Chold2;therefore, the output signal Vout2 is kept at a constant value while theclock signal is High.

In this manner, when the clock signal is High (when the time t satisfiest0≤t≤t1 or t2≤t≤t3), a first circuit configured of the transistor M1 andthe capacitor Chold1 is in the track mode, and a second circuitconfigured of the transistor M3 and the capacitor Chold2 is in the holdmode.

On the contrary, when the clock is Low, that is, Vck+<Vck− (when thetime t satisfies t1≤t≤t2 or t3≤t≤t4), the transistor M2 is turned OFFand the transistor M4 is turned ON; therefore, IEE1=0, and IEE2=IEE. Atthis time, the first circuit configured of the transistor M1 and thecapacitor Chold1 is in the hold mode, and the second circuit configuredof the transistor M3 and the capacitor Chold2 is in the track mode.

In other words, in this embodiment, by operating the first circuit andthe second circuit complementarily, the circuit that is to enter thetrack mode and the circuit that is to enter the hold mode can beswitched every half period Tck/2 of the clock signal.

Since, in this embodiment, the parasitic resistance and the parasiticcapacitance existing in transistors and wiring are similar to those ofthe conventional circuit configurations, the upper limit of the clockfrequency that can be inputted is the same as before. However, since thecircuit that is to enter the track mode and the circuit that is to enterthe hold mode is switched every half period Tck/2 of the clock signal asdescribed above, as compared to the conventional circuit configurationshown in FIG. 6 , despite the same conditions as before where the clocksignal with the same frequency is used, the input signal can be obtainedat half time intervals; therefore, the data rate can be doubled.Consequently, according to this embodiment, speeding up of thetrack-and-hold circuit can be achieved.

Note that, in the case where the track-and-hold circuit of thisembodiment is connected to an ADC in a latter part, an ADC with theoutput signal Vout1 as the input and an ADC with the output terminalVout2 as the input may be separately provided, and digital signalsoutputted from the two ADCs may be synthesized.

In addition, a multiplexer may be provided between the track-and-holdcircuit of this embodiment and an ADC, and thereby the multiplexer maybe switched to always select and output one of the output signals Vout1and Vout2, which is synchronous to the clock signal and in the hold modestate, to the ADC.

Second Embodiment

Next, a second embodiment of the present invention will be described.FIG. 3 is a circuit diagram showing a configuration of a track-and-holdcircuit related to the second embodiment of the present invention. Thetrack-and-hold circuit of this embodiment includes: a bipolar transistorM1, in which a base is connected to a positive-phase signal inputterminal (Vin+), a power supply voltage VCC is applied to a collector,and an emitter is connected to a first positive-phase signal outputterminal (Vout1+); a bipolar transistor M2, in which a base is connectedto a positive-phase clock input terminal (Vck+), and a collector isconnected to the emitter of the bipolar transistor M1; a bipolartransistor M3, in which a base is connected to the positive-phase signalinput terminal (Vin+), the power supply voltage VCC is applied to acollector, and an emitter is connected to a second positive-phase signaloutput terminal (Vout2+); a bipolar transistor M4, in which a base isconnected to a negative-phase clock input terminal (Vck−), and acollector is connected to the emitter of the bipolar transistor M3; abipolar transistor M5, in which a base is connected to a negative-phasesignal input terminal (Vin−), the power supply voltage VCC is applied toa collector, and an emitter is connected to a first negative-phasesignal output terminal (Vout1−); a bipolar transistor M6, in which abase is connected to the positive-phase clock input terminal (Vck+), anda collector is connected to the emitter of the bipolar transistor M5; abipolar transistor M7, in which a base is connected to thenegative-phase signal input terminal (Vin−), the power supply voltageVCC is applied to a collector, and an emitter is connected to a secondnegative-phase signal output terminal (Vout2−); and a bipolar transistorM8, in which a base is connected to the negative-phase clock inputterminal (Vck−), and a collector is connected to the emitter of thebipolar transistor M7.

Further, the track-and-hold circuit also includes: a capacitor Chold1,one end of which is connected to the collector of the bipolar transistorM1 and the other end of which is connected to the emitter of the bipolartransistor M1; a capacitor Chold2, one end of which is connected to thecollector of the bipolar transistor M3 and the other end of which isconnected to the emitter of the bipolar transistor M3; a capacitorChold3, one end of which is connected to the collector of the bipolartransistor M5 and the other end of which is connected to the emitter ofthe bipolar transistor M5; a capacitor Chold4, one end of which isconnected to the collector of the bipolar transistor M7 and the otherend of which is connected to the emitter of the bipolar transistor M7;and a constant current source IS, one end of which is connected to theemitters of the bipolar transistors M2, M4, M6, and M8 and the other endof which is connected to a power supply voltage VEE.

The transistors M2, M4, M6, and M8 constitute a switch circuit SW2 thatalternately turns a first differential circuit configured of thetransistors M1 and M5 and a second differential circuit configured ofthe transistors M3 and M7 to the ON state in response to thedifferential clock signals Vck+ and Vck−.

The basic operation of the track-and-hold circuit in FIG. 3 will bedescribed using FIGS. 4A to 4F. Here, the waveforms of differentialoutput signals Vout1+ and Vout1−, when the differential clock signalsVck+ and Vck− with a period Tck shown in FIG. 4 and differential inputsignals Vin+ and Vin− shown in FIGS. 4B and 4C are applied to thetrack-and-hold circuit, are shown in FIGS. 4D and 4E, and the waveformsof the differential output signals Vout2+ and Vout2− at that time areshown in FIGS. 4F and 4G.

When the clock signal is High, that is, Vck+>Vck− (when the time tsatisfies t0≤t≤t1 or t2≤t≤t3), the transistors M2 and M6 are ON, thetransistors M4 and M8 are OFF, and the PN junction between the base andthe emitter of the transistors M1 and M5 is in the ON state; therefore,the emitter voltage of the transistor M1 (the output signal Vout1+)follows the input signal Vin+ and the emitter voltage of transistor M5(the output signal Vout1−) follows the input signal Vin−.

On the other hand, since no current flows to the transistors M3, M4, M7,and M8, the PN junction between the base and the emitter of each of thetransistors M3 and M7 is in the OFF state, and the base and the emitterof each of the transistors M3 and M7 are electrically separated. At thistime, the emitter voltage of the transistor M3 (the output signalVout2+) at the moment when the clock signal changes from Low to High isretained in the capacitor Chold2; therefore, the output signal Vout2+ iskept at a constant value while the clock signal is High. Similarly, theemitter voltage of the transistor M7 (the output signal Vout2−) at themoment when the clock signal changes from Low to High is retained in thecapacitor Chold4; therefore, the output signal Vout2− is kept at aconstant value while the clock signal is High.

In this manner, when the clock signal is High (when the time t satisfiest0≤t≤t1 or t2≤t≤t3), a first differential circuit configured of thetransistors M1, M5 and the capacitors Chold1, Chold3 is in the trackmode, and a second differential circuit configured of the transistorsM3, M7 and the capacitors Chold2, Chold4 is in the hold mode.

On the contrary, when a clock is Low, that is, Vck+<Vck− (when the timet satisfies t1≤t≤t2 or t3≤t≤t4), the transistors M2 and M6 are OFF andthe transistors M4 and M8 are ON. At this time, the first differentialcircuit configured of the transistors M1, M5 and the capacitors Chold1,Chold3 is in the hold mode, and the second differential circuitconfigured of the transistors M3, M7 and the capacitors Chold2, Chold4is in the track mode.

In other words, in this embodiment, by operating the first differentialcircuit and the second differential circuit complementarily, thedifferential circuit that is to enter the track mode and thedifferential circuit that is to enter the hold mode can be switchedevery half period Tck/2 of the clock signal.

Thus, in this embodiment, the differential configuration is provided notonly to the clock-input transistor but also to the signal-inputtransistor; accordingly, it becomes possible to eliminate in-phase noiseor non-linear distortion. In addition, unification of the constantcurrent source IS as shown in FIG. 3 enables to achieve reduction inarea of the circuit scale.

Note that the connection mode between the track-and-hold circuit and theADC in the latter part is similar to that of the first embodiment. Inthe case where two ADCs are used, an ADC of a differential input typewith the differential output signals Vout1+ and Vout1− as the input andan ADC of a differential input type with the differential output signalsVout2+ and Vout2− as the input may be provided.

In the case where a multiplexer is used, a multiplexer of a differentialinput/differential output type, which selects the differential outputsignal in the hold mode state from the differential output signalsVout1+, Vout1− and the differential output signals Vout2+, Vout2− andoutputs thereof, and an ADC of the differential input type with thedifferential output signal from the multiplexer as the input may beprovided. Alternatively, a multiplexer of a differentialinput/single-phase output type that converts the differential outputsignal in the hold mode state, which is selected from the differentialoutput signals Vout1+, Vout1− and the differential output signalsVout2+, Vout2−, into a single-phase signal and outputs thereof, and anADC of a single-phase input type with the output signal from themultiplexer as the input may be provided.

The above-described embodiments merely show one case of application toassist in understanding the principles of the present invention, and theembodiments in the practical situation are allowed to have manyvariations within a scope that does not deviate from the idea of thepresent invention.

INDUSTRIAL APPLICABILITY

Embodiments of the present invention can be applied to a track-and-holdcircuit.

REFERENCE SIGNS LIST

-   -   M1 to M8 Bipolar transistor    -   Chold1 to Chold4 Capacitor    -   IS Constant current source    -   SW1, SW2 Switch circuit.

1-4. (canceled)
 5. A track-and-hold circuit comprising: a firsttransistor comprising a base connected to a signal input terminal, acollector connected to a power supply voltage, and an emitter connectedto a first signal output terminal; a second transistor comprising a baseis connected to the signal input terminal, a collector connected to thepower supply voltage, and an emitter connected to a second signal outputterminal; a first capacitor comprising a first end connected to thecollector of the first transistor and a second end connected to theemitter of the first transistor; a second capacitor comprising a firstend connected to the collector of the second transistor a second endconnected to the emitter of the second transistor; a constant currentsource configured to supply a constant current to the first transistorand the second transistor; and a switch circuit connected between theemitter of the first transistor and the constant current source, theswitch circuit being further connected between the emitter of the secondtransistor and the constant current source, the switch circuit beingconfigured to alternately turn the first transistor and the secondtransistor to an ON state in response to differential clock signals. 6.The track-and-hold circuit according to claim 5, wherein the switchcircuit comprises: a third transistor comprising a base connected to apositive-phase clock input terminal, a collector connected to theemitter of the first transistor, and an emitter connected to theconstant current source.
 7. The track-and-hold circuit according toclaim 6, wherein the switch circuit further comprises: a fourthtransistor comprising a base connected to a negative-phase clock inputterminal, a collector connected to the emitter of the second transistor,and an emitter connected to the constant current source.
 8. Atrack-and-hold circuit comprising: a first transistor comprising a baseconnected to a positive-phase signal input terminal, a collectorconnected to a power supply voltage, and an emitter connected to a firstpositive-phase signal output terminal; a second transistor comprising abase connected to a negative-phase signal input terminal, a collectorconnected to the power supply voltage, and an emitter connected to afirst negative-phase signal output terminal; a third transistorcomprising a base connected to the positive-phase signal input terminal,a collector connected to the power supply voltage, and an emitterconnected to a second positive-phase signal output terminal; a fourthtransistor comprising a base connected to the negative-phase signalinput terminal, a collector connected to the power supply voltage, andan emitter connected to a second negative-phase signal output terminal;a first capacitor comprising a first end connected to the collector ofthe first transistor and a second end connected to the emitter of thefirst transistor; a second capacitor comprising a first end connected tothe collector of the second transistor and a second end connected to theemitter of the second transistor; a third capacitor comprising a firstend connected to the collector of the third transistor and a second endconnected to the emitter of the third transistor; a fourth capacitorcomprising a first end connected to the collector of the fourthtransistor and a second end connected to the emitter the fourthtransistor; a constant current source configured to supply a constantcurrent to the first transistor, the second transistor, the thirdtransistor, and the fourth transistor; and a switch circuit connectedbetween the emitters of the first, second, third, and fourth transistorsand the constant current source, and the switch circuit being configuredto alternately turn a first differential circuit comprising the firstand second transistors and a second differential circuit comprising thethird and fourth transistors to an ON state in response to differentialclock signals.
 9. The track-and-hold circuit according to claim 8,wherein the switch circuit comprises: a fifth transistor comprising abase connected to a positive-phase clock input terminal, a collectorconnected to the emitter of the first transistor, and an emitterconnected to the constant current source.
 10. The track-and-hold circuitaccording to claim 9, wherein the switch circuit further comprises: asixth transistor comprising a base connected to the positive-phase clockinput terminal, a collector connected to the emitter of the secondtransistor, and an emitter connected to the constant current source. 11.The track-and-hold circuit according to claim 10, wherein the switchcircuit further comprises: a seventh transistor comprising a baseconnected to a negative-phase clock input terminal, a collectorconnected to the emitter of the third transistor, and an emitterconnected to the constant current source.
 12. The track-and-hold circuitaccording to claim 11, wherein the switch circuit further comprises: aneighth transistor comprising a base connected to the negative-phaseclock input terminal, a collector connected to the emitter of the fourthtransistor, and an emitter connected to the constant current source. 13.A track-and-hold circuit comprising: a first transistor comprising abase connected to a signal input terminal, a collector connected to apower supply voltage, and an emitter connected to a first signal outputterminal; a second transistor comprising a base is connected to thesignal input terminal, a collector connected to the power supplyvoltage, and an emitter connected to a second signal output terminal; aconstant current source configured to supply a constant current to thefirst transistor and the second transistor; and a switch circuitconnected between the emitter of the first transistor and the constantcurrent source, the switch circuit being further connected between theemitter of the second transistor and the constant current source, theswitch circuit being configured to alternately turn the first transistorand the second transistor to an ON state in response to differentialclock signals.
 14. The track-and-hold circuit according to claim 13further comprising: a first capacitor comprising a first end connectedto the collector of the first transistor and a second end connected tothe emitter of the first transistor.
 15. The track-and-hold circuitaccording to claim 13 further comprising: a second capacitor comprisinga first end connected to the collector of the second transistor a secondend connected to the emitter of the second transistor.
 16. Thetrack-and-hold circuit according to claim 13, wherein the switch circuitcomprises: a third transistor comprising a base connected to apositive-phase clock input terminal, a collector connected to theemitter of the first transistor, and an emitter connected to theconstant current source.
 17. The track-and-hold circuit according toclaim 16, wherein the switch circuit further comprises: a fourthtransistor comprising a base connected to a negative-phase clock inputterminal, a collector connected to the emitter of the second transistor,and an emitter connected to the constant current source.